High performance transistors can be implemented as silicon-on-insulator (SOI) semiconductor structures. The advantages of SOI technology follow from the ideal isolation between devices that are formed in separate semiconductor active layers that are islands on a common insulator (silicon dioxide) layer. Planar transistor structures formed in an SOI island are still limited in their performance by the presence of a PN junction between the source or drain and the surrounding semiconductor material. This last disadvantage is removed by the source-channel-drain structure as a three-dimensional monolithic membrane resting on the insulator layer and otherwise not touching any other semiconductor material. All the semiconductor (silicon) material is removed (etched away) except for the source-channel-drain elements. Because of the vertical protrusion of the source, channel, drain and gate of such three-dimensional devices above the insulator layer, such a structure can be referred to as a vertical transistor, and is described in Huff et al., “An Analytical Look at Vertical Transistor Structures”, Solid State Technology, August 2004, pages 59-72. The height of such a structure above the insulator layer is equal to the thickness of the SOI silicon layer overlying the insulator layer. A gate is formed around the vertical sides and the top surface of the channel as an elongate 3-dimensional membrane transverse to the channel. Thus, each transistor principally consists of an elongate source-channel-drain membrane and an elongate gate membrane transverse to the channel membrane and essentially surrounding (on three sides) a portion of the channel membrane.
Because the vertical height of a vertical transistor is so great relative to its length and width, the source, drain and gate must be doped in such a manner that dopants are introduced through top surface and through the vertical side walls of the source-channel-drain membrane and the gate membrane. One way of accomplishing this may be to perform a dopant ion implantation step in three dimensions by tilting (rotating) the wafer during ion implantation about several axes so that the ions impinge on every vertical face of the vertical transistor structure. However, this technique is not ideal because nearby or neighboring vertical transistor structures may shadow some of the surfaces during ion implantation.
What is needed is a way of doping the source, drain and gate of a vertical transistor that avoids shadowing effects while providing a uniform distribution of dopant atoms throughout the source, drain and gate at high dopant concentrations.